`timescale 1ns/1ps
module tb();
	bit clk ;
	bit rst ;
	logic singal ;
	logic posedge_checked ;
	logic negedge_checked ;
	initial begin
		clk <= 0 ;
		rst <= 1 ;
		singal <= 0 ;
		#10 ;
		rst <= 0;
		#4;
		singal <= 0;
		@(posedge clk);
		singal <= 1 ;
		@(posedge clk);
		singal <= 0 ;
		#100 ;
		$finish; 
	end
	always #2 clk = ~clk ;

	edge_check inst_edge_check
	(
		.clk             (clk),
		.rst             (rst),
		.singal          (singal),
		.posedge_checked (posedge_checked),
		.negedge_checked (negedge_checked)
	);


	initial begin
		$dumpfile("wave.vcd" );
		$dumpvars(0, tb ) ;
	end

endmodule // tb